diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 1e017d0ad2c14e5c52ad7c143257b06e421082c7..0581bce17da2d40b22eec060aa3648b292a82293 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -2485,6 +2485,9 @@
 			[KVM,ARM] Allow use of GICv4 for direct injection of
 			LPIs.
 
+	kvm-arm.ipiv_enabled=
+			[KVM,ARM] Allow use of HiSilicon ipiv on GICv4.1
+
 	kvm-arm.dvmbm_enabled=
 			[KVM,ARM] Allow use of HiSilicon DVMBM capability.
 
diff --git a/Documentation/virt/kvm/arm/pvsgi.rst b/Documentation/virt/kvm/arm/pvsgi.rst
new file mode 100644
index 0000000000000000000000000000000000000000..5f12a3aaccd2d7f9ec24553a653b40747b13eae7
--- /dev/null
+++ b/Documentation/virt/kvm/arm/pvsgi.rst
@@ -0,0 +1,33 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+Paravirtualized SGI support for HiSilicon
+==========================================
+
+KVM/arm64 provides some hypervisor service calls to support a paravirtualized
+SGI(software generated interrupt) in HiSilicon Hip12 SoC.
+
+Some SMCCC compatible hypercalls are defined:
+
+* PV_SGI_FEATURES:      0xC6000090
+* PV_SGI_ENABLE:        0xC6000091
+
+The existence of the PV_SGI hypercall should be probed using the SMCCC 1.1
+ARCH_FEATURES mechanism before calling it.
+
+PV_SGI_FEATURES
+
+    ============= ========    ==========
+    Function ID:  (uint32)    0xC6000090
+    PV_call_id:   (uint32)    The function to query for support.
+                              Currently only PV_SGI_ENABLE is supported.
+    Return value: (int64)     NOT_SUPPORTED (-1) or SUCCESS (0) if the relevant
+                              PV-sgi feature is supported by the hypervisor.
+    ============= ========    ==========
+
+PV_SGI_ENABLE
+
+    ============= ========    ==========
+    Function ID:  (uint32)    0xC6000091
+    Return value: (int64)     NOT_SUPPORTED (-1) or SUCCESS (0) if this feature
+                              has been enabled.
+    ============= ========    ==========
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 0f1accb7355f18ba2e2f5024b498957b17333d17..3a6ea88e112327ba0df7552b4faafc47e547dce6 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1990,6 +1990,19 @@ config ARM64_EPAN
 	 if the cpu does not implement the feature.
 endmenu
 
+config ARM64_HISI_IPIV
+	bool "Enable support for IPIV"
+	default y
+	depends on ACPI
+	depends on ARM64
+	help
+	  IPIV optimizes vSGI on the basis of GICv4.1. The vCPU on the sending
+	  side of vSGI needs to trap to Hypervisor. IPIv sends vSGI without
+	  traping, improving performance.
+
+	  The feature will only be enabled if CPU in the system and Guest OS
+	  support this feature. If unsure, say Y.
+
 config ARM64_SVE
 	bool "ARM Scalable Vector Extension support"
 	default y
diff --git a/arch/arm64/configs/openeuler_defconfig b/arch/arm64/configs/openeuler_defconfig
index d190cc0cb0302dd1fa45d7e597e9eb79a05ded45..3bf8a4985701e401f86d92893f5683ef3190f273 100644
--- a/arch/arm64/configs/openeuler_defconfig
+++ b/arch/arm64/configs/openeuler_defconfig
@@ -548,6 +548,7 @@ CONFIG_ARM64_TWED=y
 CONFIG_ARM64_EPAN=y
 # end of ARMv8.7 architectural features
 
+CONFIG_ARM64_HISI_IPIV=y
 CONFIG_ARM64_SVE=y
 CONFIG_ARM64_SME=y
 CONFIG_ARM64_MODULE_PLTS=y
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index afcad77b581aa68e83d1183c5fcfe88347c8bc0d..d33a5dac46428030e4ddc4d4d0e50fcba7dd2265 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -73,6 +73,11 @@ bool kvm_ncsnp_support;
 /* Capability of DVMBM */
 bool kvm_dvmbm_support;
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+/* Capability of IPIV */
+bool kvm_ipiv_support;
+#endif /* CONFIG_ARM64_HISI_IPIV */
+
 static DEFINE_PER_CPU(unsigned char, kvm_arm_hardware_enabled);
 DEFINE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
 
@@ -150,6 +155,14 @@ int kvm_arch_check_processor_compat(void *opaque)
 	return 0;
 }
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+static int kvm_hisi_ipiv_enable_cap(struct kvm *kvm, struct kvm_enable_cap *cap)
+{
+	kvm->arch.vgic.its_vm.enable_ipiv_from_vmm = true;
+	return 0;
+}
+#endif
+
 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
 			    struct kvm_enable_cap *cap)
 {
@@ -168,6 +181,11 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
 		if (static_branch_unlikely(&kvm_cvm_is_available))
 			r = kvm_cvm_enable_cap(kvm, cap);
 		break;
+#endif
+#ifdef CONFIG_ARM64_HISI_IPIV
+	case KVM_CAP_ARM_HISI_IPIV:
+		r = kvm_hisi_ipiv_enable_cap(kvm, cap);
+		break;
 #endif
 	default:
 		r = -EINVAL;
@@ -299,6 +317,10 @@ void kvm_arch_destroy_vm(struct kvm *kvm)
 #endif
 }
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+extern struct static_key_false ipiv_enable;
+#endif
+
 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
 {
 	int r;
@@ -370,6 +392,14 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
 		}
 		r = static_key_enabled(&kvm_cvm_is_available);
 		break;
+#endif
+#ifdef CONFIG_ARM64_HISI_IPIV
+	case KVM_CAP_ARM_HISI_IPIV:
+		if (static_branch_unlikely(&ipiv_enable))
+			r = 1;
+		else
+			r = 0;
+		break;
 #endif
 	default:
 		r = kvm_arch_vm_ioctl_check_extension(kvm, ext);
@@ -1298,6 +1328,16 @@ static int kvm_vcpu_set_target(struct kvm_vcpu *vcpu,
 	if (vcpu->arch.target != -1 && vcpu->arch.target != init->target)
 		return -EINVAL;
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+	if (static_branch_unlikely(&ipiv_enable) &&
+	    vcpu->kvm->arch.vgic.its_vm.enable_ipiv_from_vmm &&
+	    vcpu->vcpu_id != vcpu->vcpu_idx) {
+		kvm_err("IPIV ERROR: vcpu_id %d != vcpu_idx %d\n",
+					vcpu->vcpu_id, vcpu->vcpu_idx);
+		return -EINVAL;
+	}
+#endif
+
 	/* -ENOENT for unknown features, -EINVAL for invalid combinations. */
 	for (i = 0; i < sizeof(init->features) * 8; i++) {
 		bool set = (init->features[i / 32] & (1 << (i % 32)));
@@ -2138,6 +2178,7 @@ int kvm_arch_init(void *opaque)
 	kvm_dvmbm_support = hisi_dvmbm_supported();
 	if (kvm_dvmbm_support)
 		kvm_get_pg_cfg();
+
 #endif
 	kvm_info("KVM ncsnp %s\n", kvm_ncsnp_support ? "enabled" : "disabled");
 	kvm_info("KVM dvmbm %s\n", kvm_dvmbm_support ? "enabled" : "disabled");
diff --git a/arch/arm64/kvm/hisilicon/hisi_virt.c b/arch/arm64/kvm/hisilicon/hisi_virt.c
index e24797729fc1eeacaac2ab6beced61e95c574ebf..b324020d97eb1153701ef302a7aa66016945cfa0 100644
--- a/arch/arm64/kvm/hisilicon/hisi_virt.c
+++ b/arch/arm64/kvm/hisilicon/hisi_virt.c
@@ -11,16 +11,22 @@
 #include <asm/kvm_tmi.h>
 #endif
 #include "hisi_virt.h"
+#include <linux/bitfield.h>
 
 static enum hisi_cpu_type cpu_type = UNKNOWN_HI_TYPE;
 
 static bool dvmbm_enabled;
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+static bool ipiv_enabled;
+#endif
+
 static const char * const hisi_cpu_type_str[] = {
 	"Hisi1612",
 	"Hisi1616",
 	"Hisi1620",
 	"HIP09",
+	"HIP12",
 	"Unknown"
 };
 
@@ -29,7 +35,8 @@ static const char * const oem_str[] = {
 	"HIP06",	/* Hisi 1612 */
 	"HIP07",	/* Hisi 1616 */
 	"HIP08",	/* Hisi 1620 */
-	"HIP09"		/* HIP09 */
+	"HIP09",	/* HIP09 */
+	"HIP12"		/* HIP12 */
 };
 
 /*
@@ -154,21 +161,94 @@ static void hardware_disable_dvmbm(void *data)
 	write_sysreg_s(val, SYS_LSUDVM_CTRL_EL2);
 }
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+static int __init early_ipiv_enable(char *buf)
+{
+	return strtobool(buf, &ipiv_enabled);
+}
+early_param("kvm-arm.ipiv_enabled", early_ipiv_enable);
+
+bool hisi_ipiv_supported(void)
+{
+	if (cpu_type != HI_IP12)
+		return false;
+
+	/* Determine whether IPIV is supported by the hardware */
+	if (!(read_sysreg(aidr_el1) & AIDR_EL1_IPIV_MASK)) {
+		kvm_info("Hisi ipiv not supported by the hardware\n");
+		return false;
+	}
+
+	if (!gic_get_ipiv_status()) {
+		kvm_info("Hisi ipiv is disabled by BIOS\n");
+		return false;
+	}
+
+	/* User provided kernel command-line parameter */
+	if (!ipiv_enabled || !is_kernel_in_hyp_mode())
+		return false;
+
+	/* Enable IPIV feature if necessary */
+	if (!kvm_vgic_global_state.has_gicv4_1) {
+		kvm_info("Hisi ipiv needs to enable GICv4p1!\n");
+		return false;
+	}
+
+	kvm_info("Enable Hisi ipiv, do not support vSGI broadcast\n");
+	return true;
+}
+
+extern struct static_key_false ipiv_enable;
+
+bool hisi_ipiv_supported_per_vm(struct kvm_vcpu *vcpu)
+{
+	/* IPIV is supported by the hardware */
+	if (!static_branch_unlikely(&ipiv_enable))
+		return false;
+
+	/* vSGI passthrough is configured */
+	if (!vcpu->kvm->arch.vgic.nassgireq)
+		return false;
+
+	/* IPIV is enabled by the user */
+	if (!vcpu->kvm->arch.vgic.its_vm.enable_ipiv_from_vmm)
+		return false;
+
+	return true;
+}
+
+void hisi_ipiv_enable_per_vm(struct kvm_vcpu *vcpu)
+{
+	/* Enable IPIV feature */
+	vcpu->kvm->arch.vgic.its_vm.enable_ipiv_from_guest = true;
+}
+
+void ipiv_gicd_init(void)
+{
+	gic_dist_enable_ipiv();
+}
+#endif /* CONFIG_ARM64_HISI_IPIV */
+
 bool hisi_dvmbm_supported(void)
 {
 #ifdef CONFIG_CVM_HOST
 	if (static_branch_unlikely(&kvm_cvm_is_enable))
 		return false;
 #endif
-	if (cpu_type != HI_IP09)
+	if (cpu_type != HI_IP09 && cpu_type != HI_IP12)
 		return false;
 
+	if (!is_kernel_in_hyp_mode()) {
+		kvm_info("Hisi dvmbm not supported by KVM nVHE mode\n");
+		return false;
+	}
+
 	/* Determine whether DVMBM is supported by the hardware */
 	if (!(read_sysreg(aidr_el1) & AIDR_EL1_DVMBM_MASK))
 		return false;
 
 	/* User provided kernel command-line parameter */
-	if (!dvmbm_enabled || !is_kernel_in_hyp_mode()) {
+	if (!dvmbm_enabled) {
 		on_each_cpu(hardware_disable_dvmbm, NULL, 1);
 		return false;
 	}
@@ -187,9 +267,14 @@ int kvm_hisi_dvmbm_vcpu_init(struct kvm_vcpu *vcpu)
 		return 0;
 
 	vcpu->arch.cpus_ptr = kzalloc(sizeof(cpumask_t), GFP_ATOMIC);
+	if (!vcpu->arch.cpus_ptr)
+		return -ENOMEM;
+
 	vcpu->arch.pre_cpus_ptr = kzalloc(sizeof(cpumask_t), GFP_ATOMIC);
-	if (!vcpu->arch.cpus_ptr || !vcpu->arch.pre_cpus_ptr)
+	if (!vcpu->arch.pre_cpus_ptr) {
+		kfree(vcpu->arch.cpus_ptr);
 		return -ENOMEM;
+	}
 
 	return 0;
 }
@@ -396,6 +481,74 @@ static void kvm_update_vm_lsudvmbm(struct kvm *kvm)
 	kvm->arch.lsudvmbm_el2 = val;
 }
 
+static u64 convert_aff3_to_die_hip12(u64 aff3)
+{
+	/*
+	 * On HIP12, we use 4 bits to represent a die in SYS_LSUDVMBM_EL2.
+	 *
+	 * die1: socket ID (bits[60:59]) + die ID (bits[58:57])
+	 * die2: socket ID (bits[56:55]) + die ID (bits[54:53])
+	 *
+	 * We therefore need to properly encode Aff3 into it.
+	 */
+	return FIELD_GET(MPIDR_AFF3_SOCKET_ID_MASK, aff3) << 2 |
+	       FIELD_GET(MPIDR_AFF3_DIE_ID_MASK, aff3);
+}
+
+static void kvm_update_vm_lsudvmbm_hip12(struct kvm *kvm)
+{
+	u64 mpidr, aff3, aff2;
+	u64 vm_aff3s[DVMBM_MAX_DIES_HIP12];
+	u64 val;
+	int cpu, nr_dies;
+	u64 die1, die2;
+
+	nr_dies = kvm_dvmbm_get_dies_info(kvm, vm_aff3s, DVMBM_MAX_DIES_HIP12);
+	if (nr_dies > 2) {
+		val = DVMBM_RANGE_ALL_DIES << DVMBM_RANGE_SHIFT;
+		goto out_update;
+	}
+
+	if (nr_dies == 1) {
+		die1 = convert_aff3_to_die_hip12(vm_aff3s[0]);
+		val = DVMBM_RANGE_ONE_DIE << DVMBM_RANGE_SHIFT	|
+		      die1 << DVMBM_DIE1_SHIFT_HIP12;
+
+		/* fulfill bits [11:6] */
+		for_each_cpu(cpu, kvm->arch.dvm_cpumask) {
+			mpidr = cpu_logical_map(cpu);
+			aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);
+
+			val |= 1ULL << (aff2 + DVMBM_DIE1_CLUSTER_SHIFT_HIP12);
+		}
+
+		goto out_update;
+	}
+
+	/* nr_dies == 2 */
+	die1 = convert_aff3_to_die_hip12(vm_aff3s[0]);
+	die2 = convert_aff3_to_die_hip12(vm_aff3s[1]);
+	val = DVMBM_RANGE_TWO_DIES << DVMBM_RANGE_SHIFT	|
+	      DVMBM_GRAN_CLUSTER << DVMBM_GRAN_SHIFT	|
+	      die1 << DVMBM_DIE1_SHIFT_HIP12		|
+	      die2 << DVMBM_DIE2_SHIFT_HIP12;
+
+	/* and fulfill bits [11:0] */
+	for_each_cpu(cpu, kvm->arch.dvm_cpumask) {
+		mpidr = cpu_logical_map(cpu);
+		aff3 = MPIDR_AFFINITY_LEVEL(mpidr, 3);
+		aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);
+
+		if (aff3 == vm_aff3s[0])
+			val |= 1ULL << (aff2 + DVMBM_DIE1_CLUSTER_SHIFT_HIP12);
+		else
+			val |= 1ULL << (aff2 + DVMBM_DIE2_CLUSTER_SHIFT_HIP12);
+	}
+
+out_update:
+	kvm->arch.lsudvmbm_el2 = val;
+}
+
 void kvm_hisi_dvmbm_load(struct kvm_vcpu *vcpu)
 {
 	struct kvm *kvm = vcpu->kvm;
@@ -444,7 +597,10 @@ void kvm_hisi_dvmbm_load(struct kvm_vcpu *vcpu)
 	 * Re-calculate LSUDVMBM_EL2 for this VM and kick all vcpus
 	 * out to reload the LSUDVMBM configuration.
 	 */
-	kvm_update_vm_lsudvmbm(kvm);
+	if (cpu_type == HI_IP12)
+		kvm_update_vm_lsudvmbm_hip12(kvm);
+	else
+		kvm_update_vm_lsudvmbm(kvm);
 	kvm_make_all_cpus_request(kvm, KVM_REQ_RELOAD_DVMBM);
 
 out_unlock:
@@ -474,6 +630,9 @@ void kvm_get_pg_cfg(void)
 	u64 mn_phy_base;
 	u32 val;
 
+	if (cpu_type == HI_IP12)
+		return;
+
 	socket_num = kvm_get_socket_num();
 	die_num = kvm_get_die_num();
 
diff --git a/arch/arm64/kvm/hisilicon/hisi_virt.h b/arch/arm64/kvm/hisilicon/hisi_virt.h
index 58fb2353b67166d2292d2d8759f523b6d1e4bb98..62bf1c235adea42f6e3edfe359ae1fa4226c283a 100644
--- a/arch/arm64/kvm/hisilicon/hisi_virt.h
+++ b/arch/arm64/kvm/hisilicon/hisi_virt.h
@@ -11,9 +11,14 @@ enum hisi_cpu_type {
 	HI_1616,
 	HI_1620,
 	HI_IP09,
+	HI_IP12,
 	UNKNOWN_HI_TYPE
 };
 
+/* HIP12 */
+#ifdef CONFIG_ARM64_HISI_IPIV
+#define AIDR_EL1_IPIV_MASK	GENMASK_ULL(17, 16)
+#endif
 /* HIP09 */
 #define AIDR_EL1_DVMBM_MASK	GENMASK_ULL(13, 12)
 #define SYS_LSUDVM_CTRL_EL2	sys_reg(3, 4, 15, 7, 4)
@@ -61,9 +66,37 @@ enum hisi_cpu_type {
 
 #define DVMBM_MAX_DIES			32
 
+/*
+ * MPIDR_EL1 layout on HIP12
+ *
+ * Aff3[4:3]	- socket ID	[0-3]
+ * Aff3[2:0]	- die ID	[0,1]
+ * Aff2[2:0]	- cluster ID	[0-5]
+ * Aff1[3:0]	- core ID	[0-15]
+ * Aff0[0]	- thread ID	[0,1]
+ *
+ * On HIP12, cpu die is named as vdie. Actually,
+ * vdie is equivalent to cpu die. Here use die
+ * to describe vdie.
+ */
+
+#define MPIDR_AFF3_SOCKET_ID_MASK		GENMASK(4, 3)
+#define MPIDR_AFF3_DIE_ID_MASK			GENMASK(2, 0)
+#define DVMBM_DIE1_SHIFT_HIP12			57
+#define DVMBM_DIE2_SHIFT_HIP12			53
+#define DVMBM_DIE1_CLUSTER_SHIFT_HIP12		6
+#define DVMBM_DIE2_CLUSTER_SHIFT_HIP12		0
+#define DVMBM_MAX_DIES_HIP12			8
+
 void probe_hisi_cpu_type(void);
 bool hisi_ncsnp_supported(void);
 bool hisi_dvmbm_supported(void);
+#ifdef CONFIG_ARM64_HISI_IPIV
+bool hisi_ipiv_supported(void);
+bool hisi_ipiv_supported_per_vm(struct kvm_vcpu *vcpu);
+void hisi_ipiv_enable_per_vm(struct kvm_vcpu *vcpu);
+void ipiv_gicd_init(void);
+#endif /* CONFIG_ARM64_HISI_IPIV */
 void kvm_get_pg_cfg(void);
 
 int kvm_hisi_dvmbm_vcpu_init(struct kvm_vcpu *vcpu);
@@ -74,4 +107,8 @@ int kvm_hisi_init_dvmbm(struct kvm *kvm);
 void kvm_hisi_destroy_dvmbm(struct kvm *kvm);
 void kvm_hisi_reload_lsudvmbm(struct kvm *kvm);
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+extern void gic_dist_enable_ipiv(void);
+extern bool gic_get_ipiv_status(void);
+#endif /* CONFIG_ARM64_HISI_IPIV */
 #endif /* __HISI_VIRT_H__ */
diff --git a/arch/arm64/kvm/hypercalls.c b/arch/arm64/kvm/hypercalls.c
index ae22f72c0b474e07499793fa7330ac7200d338b3..5be8484c93c23466fcac32a8f8a4b82b00a1673c 100644
--- a/arch/arm64/kvm/hypercalls.c
+++ b/arch/arm64/kvm/hypercalls.c
@@ -9,6 +9,10 @@
 #include <kvm/arm_hypercalls.h>
 #include <kvm/arm_psci.h>
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+#include "hisilicon/hisi_virt.h"
+#endif
+
 static void kvm_ptp_get_time(struct kvm_vcpu *vcpu, u64 *val)
 {
 	struct system_time_snapshot systime_snapshot;
@@ -135,6 +139,22 @@ int kvm_hvc_call_handler(struct kvm_vcpu *vcpu)
 		if (gpa != GPA_INVALID)
 			val[0] = gpa;
 		break;
+#ifdef CONFIG_ARM64_HISI_IPIV
+	case ARM_SMCCC_VENDOR_PV_SGI_FEATURES:
+		if (hisi_ipiv_supported_per_vm(vcpu))
+			val[0] = SMCCC_RET_SUCCESS;
+		else
+			val[0] = SMCCC_RET_NOT_SUPPORTED;
+		break;
+	case ARM_SMCCC_VENDOR_PV_SGI_ENABLE:
+		if (hisi_ipiv_supported_per_vm(vcpu)) {
+			hisi_ipiv_enable_per_vm(vcpu);
+			val[0] = SMCCC_RET_SUCCESS;
+		} else {
+			val[0] = SMCCC_RET_NOT_SUPPORTED;
+		}
+		break;
+#endif
 	case ARM_SMCCC_VENDOR_HYP_CALL_UID_FUNC_ID:
 		val[0] = ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_0;
 		val[1] = ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_1;
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 1ee3c00ed8a0e42c11e7d9681a0bb0cbfaade807..6cab93cd2b84ff9ac40501ae3b5b44812d99d689 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -662,7 +662,9 @@ static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 	mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
 	mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
 	mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
-	vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1);
+
+	mpidr |= (1ULL << 31);
+	vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1);
 }
 
 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
@@ -1282,6 +1284,29 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
 	return 0;
 }
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+extern struct static_key_false ipiv_enable;
+static int set_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
+		     const struct kvm_one_reg *reg, void __user *uaddr)
+{
+	u64 val;
+	if (get_user(val, (u64 __user *)uaddr))
+		return -EFAULT;
+
+	if (static_branch_unlikely(&ipiv_enable) &&
+	    vcpu->kvm->arch.vgic.its_vm.enable_ipiv_from_vmm) {
+		if (val != __vcpu_sys_reg(vcpu, rd->reg)) {
+			kvm_err("IPIV ERROR: MPIDR changed\n");
+			return -EINVAL;
+		}
+	}
+
+	__vcpu_sys_reg(vcpu, rd->reg) = val;
+
+	return 0;
+}
+#endif
+
 /*
  * cpufeature ID register user accessors
  */
@@ -1495,7 +1520,12 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 
 	{ SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+	{ SYS_DESC(SYS_MPIDR_EL1),
+	  .reset = reset_mpidr, .reg = MPIDR_EL1, .set_user = set_mpidr},
+#else
 	{ SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
+#endif
 
 	/*
 	 * ID regs: all ID_SANITISED() entries here must have corresponding
diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c
index d38c1d513768adb95a0741ea1fd906fcfa369789..925a3749f85006d874b206d87981c8f3671078ff 100644
--- a/arch/arm64/kvm/vgic/vgic-init.c
+++ b/arch/arm64/kvm/vgic/vgic-init.c
@@ -3,6 +3,7 @@
  * Copyright (C) 2015, 2016 ARM Ltd.
  */
 
+#include <linux/acpi.h>
 #include <linux/uaccess.h>
 #include <linux/interrupt.h>
 #include <linux/cpu.h>
@@ -12,6 +13,11 @@
 #include <asm/kvm_mmu.h>
 #include "vgic.h"
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+#include <linux/irqchip/arm-gic-v3.h>
+#include "hisilicon/hisi_virt.h"
+#endif
+
 /*
  * Initialization rules: there are multiple stages to the vgic
  * initialization, both for the distributor and the CPU interfaces.  The basic
@@ -457,21 +463,60 @@ int kvm_vgic_map_resources(struct kvm *kvm)
 	return ret;
 }
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+extern struct static_key_false ipiv_enable;
+static int ipiv_irq;
+#endif
+
 /* GENERIC PROBE */
 
 static int vgic_init_cpu_starting(unsigned int cpu)
 {
 	enable_percpu_irq(kvm_vgic_global_state.maint_irq, 0);
+#ifdef CONFIG_ARM64_HISI_IPIV
+	if (static_branch_unlikely(&ipiv_enable))
+		enable_percpu_irq(ipiv_irq, 0);
 	return 0;
+#endif
 }
 
 
 static int vgic_init_cpu_dying(unsigned int cpu)
 {
 	disable_percpu_irq(kvm_vgic_global_state.maint_irq);
+#ifdef CONFIG_ARM64_HISI_IPIV
+	if (static_branch_unlikely(&ipiv_enable))
+		disable_percpu_irq(ipiv_irq);
 	return 0;
+#endif
 }
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+extern void __iomem *gic_data_rdist_get_vlpi_base(void);
+static irqreturn_t vgic_ipiv_irq_handler(int irq, void *data)
+{
+	void __iomem *vlpi_base = gic_data_rdist_get_vlpi_base();
+	u32 gicr_ipiv_st;
+	bool broadcast_err, grpbrd_err, vcpuidx_err;
+
+	gicr_ipiv_st = readl_relaxed(vlpi_base + GICR_IPIV_ST);
+
+	broadcast_err = !!(gicr_ipiv_st & GICR_IPIV_ST_IRM_ERR);
+	if (broadcast_err)
+		kvm_err("IPIV error: IRM=1 Guest broadcast error\n");
+
+	grpbrd_err = !!(gicr_ipiv_st & GICR_IPIV_ST_BRPBRD_ERR);
+	if (grpbrd_err)
+		kvm_err("IPIV error: Guest group broadcast error\n");
+
+	vcpuidx_err = !!(gicr_ipiv_st & GICR_IPIV_ST_VCPUIDX_ERR);
+	if (vcpuidx_err)
+		kvm_err("IPIV error: The VCPU index is out of range\n");
+
+	return IRQ_HANDLED;
+}
+#endif
+
 static irqreturn_t vgic_maintenance_handler(int irq, void *data)
 {
 	/*
@@ -560,6 +605,37 @@ int kvm_vgic_hyp_init(void)
 	}
 
 	kvm_info("vgic interrupt IRQ%d\n", kvm_vgic_global_state.maint_irq);
+
+#ifdef CONFIG_ARM64_HISI_IPIV
+	if (hisi_ipiv_supported()) {
+		ipiv_gicd_init();
+		kvm_info("KVM ipiv enabled\n");
+	} else {
+		kvm_info("KVM ipiv disabled\n");
+	}
+
+	if (static_branch_unlikely(&ipiv_enable)) {
+		ipiv_irq = acpi_register_gsi(NULL, 18, ACPI_EDGE_SENSITIVE,
+			ACPI_ACTIVE_HIGH);
+		if (ipiv_irq < 0) {
+			kvm_err("No ipiv exception irq\n");
+			free_percpu_irq(kvm_vgic_global_state.maint_irq,
+					kvm_get_running_vcpus());
+			return -ENXIO;
+		}
+
+		ret = request_percpu_irq(ipiv_irq, vgic_ipiv_irq_handler,
+				 "ipiv exception", kvm_get_running_vcpus());
+		if (ret) {
+			kvm_err("Cannot register interrupt %d\n", ipiv_irq);
+			free_percpu_irq(kvm_vgic_global_state.maint_irq,
+					kvm_get_running_vcpus());
+			acpi_unregister_gsi(18);
+			return ret;
+		}
+	}
+#endif
+
 	return 0;
 
 out_free_irq:
diff --git a/arch/arm64/kvm/vgic/vgic-its.c b/arch/arm64/kvm/vgic/vgic-its.c
index 4805a12e06169fd04cbb574ddc167097fcf42fff..86e3914e3148c64b594ace61471f02cca913a9cc 100644
--- a/arch/arm64/kvm/vgic/vgic-its.c
+++ b/arch/arm64/kvm/vgic/vgic-its.c
@@ -498,6 +498,14 @@ static unsigned long vgic_mmio_read_its_typer(struct kvm *kvm,
 	return extract_bytes(reg, addr & 7, len);
 }
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+/*
+ * Use bit7 not used by GITS_IIDR to indicate whether IPIV is
+ * enabled for guest OS.
+ */
+#define HISI_GUEST_ENABLE_IPIV_SHIFT 7
+#endif
+
 static unsigned long vgic_mmio_read_its_iidr(struct kvm *kvm,
 					     struct vgic_its *its,
 					     gpa_t addr, unsigned int len)
@@ -518,6 +526,12 @@ static int vgic_mmio_uaccess_write_its_iidr(struct kvm *kvm,
 
 	if (rev >= NR_ITS_ABIS)
 		return -EINVAL;
+
+#ifdef CONFIG_ARM64_HISI_IPIV
+	if (val & (1UL << HISI_GUEST_ENABLE_IPIV_SHIFT))
+		kvm->arch.vgic.its_vm.enable_ipiv_from_guest = true;
+#endif
+
 	return vgic_its_set_abi(its, rev);
 }
 
@@ -2108,6 +2122,11 @@ static int vgic_its_attr_regs_access(struct kvm_device *dev,
 			region->its_write(dev->kvm, its, addr, len, *reg);
 	} else {
 		*reg = region->its_read(dev->kvm, its, addr, len);
+#ifdef CONFIG_ARM64_HISI_IPIV
+		if (dev->kvm->arch.vgic.its_vm.enable_ipiv_from_guest &&
+			    offset == GITS_IIDR)
+			*reg |= 1UL << HISI_GUEST_ENABLE_IPIV_SHIFT;
+#endif
 	}
 	unlock_all_vcpus(dev->kvm);
 out:
@@ -2716,6 +2735,15 @@ static void vgic_its_reset(struct kvm *kvm, struct vgic_its *its)
 	its->enabled = 0;
 	vgic_its_free_device_list(kvm, its);
 	vgic_its_free_collection_list(kvm, its);
+
+#ifdef CONFIG_ARM64_HISI_IPIV
+	/*
+	 * For the para-virtualization feature IPIV, ensure that
+	 * the flag of the guest OS is reset when the guest OS is
+	 * reset.
+	 */
+	kvm->arch.vgic.its_vm.enable_ipiv_from_guest = false;
+#endif
 }
 
 static int vgic_its_has_attr(struct kvm_device *dev,
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 8fd053dc6aa5db9d9ce3f7ff2f38c1f7beaaa2b5..76bc12d375a26920ef36f48c5942f32c56770534 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -518,6 +518,16 @@ static int nr_gicr;
 #define gic_data_rdist_rd_base()	(gic_data_rdist()->rd_base)
 #define gic_data_rdist_vlpi_base()	(gic_data_rdist_rd_base() + SZ_128K)
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+extern struct static_key_false ipiv_enable;
+
+void __iomem *gic_data_rdist_get_vlpi_base(void)
+{
+	return gic_data_rdist_vlpi_base();
+}
+EXPORT_SYMBOL(gic_data_rdist_get_vlpi_base);
+#endif
+
 /*
  * Currently we only build *one* devid pool.
  */
@@ -4814,12 +4824,70 @@ static void its_vpe_4_1_unmask_irq(struct irq_data *d)
 	its_vpe_4_1_send_inv(d);
 }
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+/* IPIV private register */
+#define CPU_SYS_TRAP_EL2		sys_reg(3, 4, 15, 7, 2)
+#define CPU_SYS_TRAP_EL2_IPIV_ENABLE_SHIFT	0
+#define CPU_SYS_TRAP_EL2_IPIV_ENABLE		\
+	(1ULL << CPU_SYS_TRAP_EL2_IPIV_ENABLE_SHIFT)
+
+/*
+ * ipiv_disable_vsgi_trap and ipiv_enable_vsgi_trap run only
+ * in VHE mode and in EL2.
+ */
+static void ipiv_disable_vsgi_trap(void)
+{
+	u64 val;
+
+	/* disable guest access ICC_SGI1R_EL1 trap, enable ipiv */
+	val = read_sysreg_s(CPU_SYS_TRAP_EL2);
+	val |= CPU_SYS_TRAP_EL2_IPIV_ENABLE;
+	write_sysreg_s(val, CPU_SYS_TRAP_EL2);
+}
+
+static void ipiv_enable_vsgi_trap(void)
+{
+	u64 val;
+
+	/* enable guest access ICC_SGI1R_EL1 trap, disable ipiv */
+	val = read_sysreg_s(CPU_SYS_TRAP_EL2);
+	val &= ~CPU_SYS_TRAP_EL2_IPIV_ENABLE;
+	write_sysreg_s(val, CPU_SYS_TRAP_EL2);
+}
+#endif /* CONFIG_ARM64_HISI_IPIV */
+
 static void its_vpe_4_1_schedule(struct its_vpe *vpe,
 				 struct its_cmd_info *info)
 {
 	void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
 	u64 val = 0;
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+	struct its_vm *vm = vpe->its_vm;
+	unsigned long vpeid_page_addr;
+	u64 ipiv_val = 0;
+	u32 nr_vpes;
+
+	if (vm->enable_ipiv_from_guest) {
+		/* wait gicr_ipiv_busy */
+		WARN_ON_ONCE(readl_relaxed_poll_timeout_atomic(vlpi_base + GICR_IPIV_ST,
+					ipiv_val, !(ipiv_val & GICR_IPIV_ST_IPIV_BUSY), 1, 500));
+		vpeid_page_addr = virt_to_phys(page_address(vm->vpeid_page));
+		writel_relaxed(lower_32_bits(vpeid_page_addr),
+					vlpi_base + GICR_VM_TABLE_BAR_L);
+		writel_relaxed(upper_32_bits(vpeid_page_addr),
+					vlpi_base + GICR_VM_TABLE_BAR_H);
+
+		/* setup gicr_vcpu_entry_num_max and gicr_ipiv_its_ta_sel */
+		nr_vpes = vpe->its_vm->nr_vpes;
+		ipiv_val = ((nr_vpes - 1) << GICR_IPIV_CTRL_VCPU_ENTRY_NUM_MAX_SHIFT) |
+			(0 << GICR_IPIV_CTRL_IPIV_ITS_TA_SEL_SHIFT);
+		writel_relaxed(ipiv_val, vlpi_base + GICR_IPIV_CTRL);
+
+		ipiv_disable_vsgi_trap();
+	}
+#endif /* CONFIG_ARM64_HISI_IPIV */
+
 	/* Schedule the VPE */
 	val |= GICR_VPENDBASER_Valid;
 	val |= info->g0en ? GICR_VPENDBASER_4_1_VGRP0EN : 0;
@@ -4835,6 +4903,10 @@ static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
 	void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
 	u64 val;
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+	struct its_vm *vm = vpe->its_vm;
+#endif
+
 	if (info->req_db) {
 		unsigned long flags;
 
@@ -4864,6 +4936,18 @@ static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
 					    GICR_VPENDBASER_PendingLast);
 		vpe->pending_last = true;
 	}
+
+#ifdef CONFIG_ARM64_HISI_IPIV
+	if (vm->enable_ipiv_from_guest) {
+		/* wait gicr_ipiv_busy */
+		WARN_ON_ONCE(readl_relaxed_poll_timeout_atomic(vlpi_base + GICR_IPIV_ST,
+					val, !(val & GICR_IPIV_ST_IPIV_BUSY), 1, 500));
+		writel_relaxed(0, vlpi_base + GICR_VM_TABLE_BAR_L);
+		writel_relaxed(0, vlpi_base + GICR_VM_TABLE_BAR_H);
+
+		ipiv_enable_vsgi_trap();
+	}
+#endif
 }
 
 static void its_vpe_4_1_invall(struct its_vpe *vpe)
@@ -5238,6 +5322,12 @@ static void its_vpe_irq_domain_free(struct irq_domain *domain,
 	if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
 		its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
 		its_free_prop_table(vm->vprop_page);
+#ifdef CONFIG_ARM64_HISI_IPIV
+		if (vm->enable_ipiv_from_vmm) {
+			free_pages((unsigned long)page_address(vm->vpeid_page),
+				    get_order(nr_irqs * 2));
+		}
+#endif
 	}
 }
 
@@ -5250,6 +5340,12 @@ static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq
 	struct page *vprop_page;
 	int base, nr_ids, i, err = 0;
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+	struct page *vpeid_page;
+	void *vpeid_table_va;
+	u16 *vpeid_entry;
+#endif
+
 	BUG_ON(!vm);
 
 	bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
@@ -5272,14 +5368,37 @@ static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq
 	vm->nr_db_lpis = nr_ids;
 	vm->vprop_page = vprop_page;
 
-	if (gic_rdists->has_rvpeid)
+	if (gic_rdists->has_rvpeid) {
 		irqchip = &its_vpe_4_1_irq_chip;
+#ifdef CONFIG_ARM64_HISI_IPIV
+		if (vm->enable_ipiv_from_vmm) {
+			/*
+			 * The vpeid's size is 2 bytes, so we need to allocate 2 *
+			 * (num of vcpus). nr_irqs is equal to the number of vCPUs.
+			 */
+			vpeid_page = alloc_pages(GFP_KERNEL, get_order(nr_irqs * 2));
+			if (!vpeid_page) {
+				its_lpi_free(bitmap, base, nr_ids);
+				its_free_prop_table(vprop_page);
+				return -ENOMEM;
+			}
+			vm->vpeid_page = vpeid_page;
+			vpeid_table_va = page_address(vpeid_page);
+		}
+#endif
+	}
 
 	for (i = 0; i < nr_irqs; i++) {
 		vm->vpes[i]->vpe_db_lpi = base + i;
 		err = its_vpe_init(vm->vpes[i]);
 		if (err)
 			break;
+#ifdef CONFIG_ARM64_HISI_IPIV
+		if (vm->enable_ipiv_from_vmm) {
+			vpeid_entry = (u16 *)vpeid_table_va + i;
+			*vpeid_entry = vm->vpes[i]->vpe_id;
+		}
+#endif
 		err = its_irq_gic_domain_alloc(domain, virq + i,
 					       vm->vpes[i]->vpe_db_lpi);
 		if (err)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 39a854ec93cac5016088f3e6905ff2580136b633..940c58fe23741637905ebb3fc7911a9027170ac8 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -107,6 +107,15 @@ EXPORT_SYMBOL(gic_pmr_sync);
 DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities);
 EXPORT_SYMBOL(gic_nonsecure_priorities);
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+/* indicate if host supports IPIv */
+DEFINE_STATIC_KEY_FALSE(ipiv_enable);
+EXPORT_SYMBOL(ipiv_enable);
+
+/* indicate if guest is using IPIv */
+static bool hisi_pv_sgi_enabled;
+#endif
+
 /*
  * When the Non-secure world has access to group 0 interrupts (as a
  * consequence of SCR_EL3.FIQ == 0), reading the ICC_RPR_EL1 register will
@@ -1245,6 +1254,37 @@ static int gic_dist_supports_lpis(void)
 		!gicv3_nolpi);
 }
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+void gic_dist_enable_ipiv(void)
+{
+	u32 val;
+
+	static_branch_enable(&ipiv_enable);
+	val = (0 << GICD_IPIV_CTRL_AFF_DIRECT_VPEID_SHIFT) |
+		(4 << GICD_IPIV_CTRL_AFF1_LEFT_SHIFT_SHIFT) |
+		(12 << GICD_IPIV_CTRL_AFF2_LEFT_SHIFT_SHIFT) |
+		(7 << GICD_IPIV_CTRL_VM_TABLE_INNERCACHE_SHIFT) |
+		(2 << GICD_IPIV_CTRL_VM_TABLE_SHAREABILITY_SHIFT);
+	writel_relaxed(val, gic_data.dist_base + GICD_IPIV_CTRL);
+
+	/* Set target ITS address of IPIV feature */
+	writel_relaxed(0x4880, gic_data.dist_base + GICD_IPIV_ITS_TA_BASE);
+}
+EXPORT_SYMBOL(gic_dist_enable_ipiv);
+
+bool gic_get_ipiv_status(void)
+{
+	u32 val;
+
+	val = readl_relaxed(gic_data.dist_base + GICD_MISC_CTRL);
+	if (val & GICD_MISC_CTRL_CFG_IPIV_EN)
+		return true;
+
+	return false;
+}
+EXPORT_SYMBOL(gic_get_ipiv_status);
+#endif /* CONFIG_ARM64_HISI_IPIV */
+
 static void gic_cpu_init(void)
 {
 	void __iomem *rbase;
@@ -1434,7 +1474,15 @@ static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
 		u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu));
 		u16 tlist;
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+		if (!hisi_pv_sgi_enabled)
+			tlist = gic_compute_target_list(&cpu, mask, cluster_id);
+		else
+			tlist = 1 << (gic_mpidr_to_affinity(cpu_logical_map(cpu)) & 0xf);
+#else
 		tlist = gic_compute_target_list(&cpu, mask, cluster_id);
+#endif
+
 		gic_send_sgi(cluster_id, tlist, d->hwirq);
 	}
 
@@ -2544,6 +2592,28 @@ static struct fwnode_handle *gic_v3_get_gsi_domain_id(u32 gsi)
 	return gsi_domain_handle;
 }
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+static void hisi_pv_sgi_init(void)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_1_1_invoke(ARM_SMCCC_VENDOR_PV_SGI_FEATURES, &res);
+	if (res.a0 != SMCCC_RET_SUCCESS) {
+		pr_info("Not Support HiSilicon PV SGI!\n");
+		return;
+	}
+
+	arm_smccc_1_1_invoke(ARM_SMCCC_VENDOR_PV_SGI_ENABLE, &res);
+	if (res.a0 != SMCCC_RET_SUCCESS) {
+		pr_info("Disable HiSilicon PV SGI!\n");
+		return;
+	}
+
+	hisi_pv_sgi_enabled = true;
+	pr_info("Enable HiSilicon PV SGI!\n");
+}
+#endif
+
 static int __init
 gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end)
 {
@@ -2594,6 +2664,10 @@ gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end)
 	if (static_branch_likely(&supports_deactivate_key))
 		gic_acpi_setup_kvm_info();
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+	hisi_pv_sgi_init();
+#endif
+
 	return 0;
 
 out_fwhandle_free:
diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h
index 9e50a386ec8f368f7e62c49b34276df3b3085e29..655ec4854768f45c858b4a83446ef1f973aac069 100644
--- a/include/linux/arm-smccc.h
+++ b/include/linux/arm-smccc.h
@@ -522,5 +522,20 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1,
 			   ARM_SMCCC_OWNER_STANDARD_HYP,		\
 			   0x93)
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+/* HiSilicon paravirtualised sgi calls */
+#define ARM_SMCCC_VENDOR_PV_SGI_FEATURES					\
+	ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL,				\
+			   ARM_SMCCC_SMC_64,				\
+			   ARM_SMCCC_OWNER_VENDOR_HYP,			\
+			   0x90)
+
+#define ARM_SMCCC_VENDOR_PV_SGI_ENABLE					\
+	ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL,				\
+			   ARM_SMCCC_SMC_64,				\
+			   ARM_SMCCC_OWNER_VENDOR_HYP,			\
+			   0x91)
+#endif /* CONFIG_ARM64_HISI_IPIV */
+
 #endif /*__ASSEMBLY__*/
 #endif /*__LINUX_ARM_SMCCC_H*/
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index b8b723cdaaf049dfc8f34097b9244e020e90a3f8..6806aab76df48eeb85cf73b5cdd609f8fc54e305 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -110,6 +110,20 @@
 #define GIC_PAGE_SIZE_64K		2ULL
 #define GIC_PAGE_SIZE_MASK		3ULL
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+#define GICD_MISC_CTRL			0x2084
+#define GICD_MISC_CTRL_CFG_IPIV_EN	(1U << 19)
+
+/* IPIV private register */
+#define GICD_IPIV_CTRL			0xc05c
+#define GICD_IPIV_CTRL_AFF_DIRECT_VPEID_SHIFT 4
+#define GICD_IPIV_CTRL_AFF1_LEFT_SHIFT_SHIFT 8
+#define GICD_IPIV_CTRL_AFF2_LEFT_SHIFT_SHIFT 12
+#define GICD_IPIV_CTRL_VM_TABLE_INNERCACHE_SHIFT 16
+#define GICD_IPIV_CTRL_VM_TABLE_SHAREABILITY_SHIFT 19
+#define GICD_IPIV_ITS_TA_BASE	0xc010
+#endif
+
 /*
  * Re-Distributor registers, offsets from RD_base
  */
@@ -356,6 +370,29 @@
 #define GICR_VSGIPENDR_BUSY		(1U << 31)
 #define GICR_VSGIPENDR_PENDING		GENMASK(15, 0)
 
+#ifdef CONFIG_ARM64_HISI_IPIV
+/* IPIV VM table address */
+#define GICR_VM_TABLE_BAR_L		0x140
+#define GICR_VM_TABLE_BAR_H		0x144
+
+#define GICR_IPIV_CTRL		0x148
+#define GICR_IPIV_CTRL_VCPU_ENTRY_NUM_MAX_SHIFT 8
+/*
+ * Select ITS to determine the ITS through which the IPI is sent.
+ */
+#define GICR_IPIV_CTRL_IPIV_ITS_TA_SEL_SHIFT 4
+
+#define GICR_IPIV_ST		0x14c
+#define GICR_IPIV_ST_IPIV_BUSY_SHIFT 0
+#define GICR_IPIV_ST_IPIV_BUSY (1 << GICR_IPIV_ST_IPIV_BUSY_SHIFT)
+#define GICR_IPIV_ST_IRM_ERR_ST_SHIFT 1
+#define GICR_IPIV_ST_IRM_ERR   (1 << GICR_IPIV_ST_IRM_ERR_ST_SHIFT)
+#define GICR_IPIV_ST_BRPBRD_ERR_ST_SHIFT 2
+#define GICR_IPIV_ST_BRPBRD_ERR   (1 << GICR_IPIV_ST_BRPBRD_ERR_ST_SHIFT)
+#define GICR_IPIV_ST_VCPUIDX_ERR_ST_SHIFT 3
+#define GICR_IPIV_ST_VCPUIDX_ERR   (1 << GICR_IPIV_ST_VCPUIDX_ERR_ST_SHIFT)
+#endif /* CONFIG_ARM64_HISI_IPIV */
+
 /*
  * ITS registers, offsets from ITS_base
  */
diff --git a/include/linux/irqchip/arm-gic-v4.h b/include/linux/irqchip/arm-gic-v4.h
index 51c11e5a1888fb9cf18f1f8dd66b9c96187c1542..73f1a0b449e13b39e8003525d50fdf0c87137b47 100644
--- a/include/linux/irqchip/arm-gic-v4.h
+++ b/include/linux/irqchip/arm-gic-v4.h
@@ -26,6 +26,11 @@ struct its_vm {
 	unsigned long		*db_bitmap;
 	int			nr_db_lpis;
 	u32			vlpi_count[GICv4_ITS_LIST_MAX];
+#ifdef CONFIG_ARM64_HISI_IPIV
+	struct page		*vpeid_page;
+	bool			enable_ipiv_from_vmm;
+	bool			enable_ipiv_from_guest;
+#endif
 };
 
 /* Embedded in kvm_vcpu.arch */
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index f27776e44095e6be23f90d322af94f585aa17183..2ccc0d0a6406b6241c6a6b34502f146645aaad1e 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -1100,6 +1100,7 @@ struct kvm_ppc_resize_hpt {
 
 #define KVM_CAP_ARM_CPU_FEATURE 555
 
+#define KVM_CAP_ARM_HISI_IPIV 798
 #define KVM_CAP_ARM_VIRT_MSI_BYPASS 799
 #define KVM_CAP_LOONGARCH_FPU 800
 #define KVM_CAP_LOONGARCH_LSX 801